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REC-STA: Reconfigurable and Efficient Chip Design With SMO-Based Training Accelerator.

Chih-Hsiang PengBo-Wei ChenTa-Wen KuanPo-Chuan LinJhing-Fa WangNai-Sheng Shih
Published in: IEEE Trans. Very Large Scale Integr. Syst. (2014)
Keyphrases
  • chip design
  • cost effective
  • real time
  • case study
  • neural network
  • training set
  • parallel implementation
  • physical design