Model Checking Software-Defined Networks with Flow Entries that Time Out.
Vasileios KlimisGeorge ParisisBernhard ReusPublished in: CoRR (2020)
Keyphrases
- model checking
- temporal logic
- formal verification
- formal methods
- formal specification
- automated verification
- temporal properties
- model checker
- symbolic model checking
- transition systems
- finite state machines
- reactive systems
- partial order reduction
- timed automata
- epistemic logic
- verification method
- computation tree logic
- finite state
- bounded model checking
- pspace complete
- software development
- reachability analysis
- process algebra
- software components
- software architecture
- abstract interpretation
- artificial intelligence
- asynchronous circuits
- information flow
- software systems
- reinforcement learning
- web services