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A bipartition-codec architecture to reduce power in pipelinedcircuits.
Shanq-Jang Ruan
Rung-Ji Shang
Feipei Lai
Kun-Lin Tsai
Published in:
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2001)
Keyphrases
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management system
real time
power consumption
learning algorithm
software architecture
video codec
multithreading
neural network
genetic algorithm
computer vision
video coding
motion compensated
data flow
significantly reduced