A K-Band Fractional-N PLL with Low-Spur Low-Power Linearization Circuit and PVT Robust Spur Trapper.
Zexin YuanLei ZhangYan WangPublished in: ISCAS (2021)
Keyphrases
- low power
- high speed
- logic circuits
- power consumption
- low cost
- low power consumption
- cmos technology
- power reduction
- vlsi circuits
- delay insensitive
- gate array
- power dissipation
- wireless transmission
- vlsi architecture
- high power
- single chip
- mixed signal
- digital signal processing
- nm technology
- frequency response
- low voltage
- real time