FSMD partitioning for low power using simulated annealing.
Nainesh AgarwalNikitas J. DimopoulosPublished in: ISCAS (2008)
Keyphrases
- low power
- simulated annealing
- low cost
- high speed
- power consumption
- single chip
- genetic algorithm
- high power
- low power consumption
- digital signal processing
- evolutionary algorithm
- logic circuits
- wireless transmission
- cmos technology
- vlsi architecture
- real time
- image sensor
- mixed signal
- energy dissipation
- signal processor
- power reduction
- delay insensitive
- low complexity
- vlsi circuits
- gate array