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A 138Fsrms-Integrated-Jitter and -249dB-FoM Clock Multiplier with -51dBc Spur Using A Digital Spur Calibration Technique in 28-nm CMOS.
Yi-An Li
Ali M. Niknejad
Published in:
VLSI Circuits (2019)
Keyphrases
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power consumption
high speed
circuit design
metal oxide semiconductor
nm technology
database
floating point
camera calibration
packet loss
cmos technology
digital libraries
low power
hardware implementation
cmos image sensor