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Design and FPGA Implementation of High-Speed Area and Power Efficient 64-bit Modified Dual CLCG based Pseudo Random Bit Generator.
Krishna Sai Tarun Ramapragada
Ajith Kumar Reddy Netla
Pavan Kalyan Chattada
Bhaskar Manickam
Published in:
iSES (2021)
Keyphrases
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pseudorandom
fpga implementation
high speed
random numbers
uniformly distributed
random number
real time
hardware implementation
secret key
multiscale
pattern recognition
lightweight
cost effective
power consumption
efficient implementation
software development
image analysis
case study