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Efficient multiplier-free FPGA demonstration of polar-domain multi-symbol-delay-detector (MSDD) for high performance phase recovery of 16-QAM.
Alex Tolmachev
Igor Tselniker
Maxim Meltsin
Itzik Sigron
Moshe Nazarathy
Published in:
OFC/NFOEC (2013)
Keyphrases
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low cost
domain specific
cost effective
domain independent
hardware implementation
general purpose
high efficiency
signal processing
verilog hdl