Parallel Matrix Multiplication on a Linear Array with a Reconfigurable Pipelined Bus System.
Keqin LiVictor Y. PanPublished in: IEEE Trans. Computers (2001)
Keyphrases
- linear array
- matrix multiplication
- distributed memory
- processing elements
- parallel computers
- hardware implementation
- message passing
- shared memory
- parallel implementation
- low cost
- massively parallel
- field programmable gate array
- image processing
- parallel machines
- parallel processing
- parallel algorithm
- hardware architecture
- data processing
- software engineering