Error Immune Logic for Low-Power Probabilistic Computing.
Bo MarrJason GeorgeBrian P. DegnanDavid V. AndersonPaul E. HaslerPublished in: VLSI Design (2010)
Keyphrases
- low power
- logic circuits
- power consumption
- low cost
- high speed
- probabilistic logic
- delay insensitive
- high power
- vlsi architecture
- single chip
- probability theory
- low power consumption
- gate array
- wireless transmission
- real time
- power saving
- cmos technology
- power reduction
- vlsi circuits
- image sensor
- parallel processing
- computer simulation
- motion estimation
- probabilistic model