PVS: Combining Specification, Proof Checking, and Model Checking.
Natarajan ShankarPublished in: FMCAD (1996)
Keyphrases
- model checking
- formal verification
- verification method
- temporal logic
- timed automata
- formal specification
- model checker
- transition systems
- automated verification
- bounded model checking
- temporal properties
- symbolic model checking
- formal methods
- reactive systems
- partial order reduction
- process algebra
- computation tree logic
- epistemic logic
- finite state
- finite state machines
- reachability analysis
- linear temporal logic
- pspace complete
- theorem proving
- modal logic
- asynchronous circuits
- concurrent systems
- theorem prover
- situation calculus
- abstract interpretation