Distributed and low-power synchronization architecture for embedded multiprocessors.
Chenjie YuPeter PetrovPublished in: CODES+ISSS (2008)
Keyphrases
- low power
- vlsi architecture
- low cost
- power consumption
- high speed
- cmos technology
- mixed signal
- high power
- embedded systems
- single chip
- wireless transmission
- real time
- nm technology
- vlsi circuits
- digital signal processing
- logic circuits
- parallel architecture
- signal processor
- low power consumption
- multithreading
- image sensor
- delay insensitive
- digital camera
- gate array
- computing platform
- multi channel
- message passing
- peer to peer