A high-resolution pipeline time-to-digital converter in 0.18μm CMOS technology.
Yongsheng WangQiao YeHan ZhaoXiaowei LiuPublished in: ASICON (2017)
Keyphrases
- low voltage
- cmos technology
- high resolution
- mixed signal
- low power
- data conversion
- spl times
- power consumption
- super resolution
- parallel processing
- high speed
- design considerations
- multi channel
- analog to digital converter
- remote sensing
- high quality
- cmos image sensor
- image processing
- power management
- digital camera
- low cost