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Balanced loop retiming to effectively architect STT-RAM-based hybrid cache for VLIW processors.
Keni Qiu
Weigong Zhang
Xiaoqiang Wu
Xiaoyan Zhu
Jing Wang
Yuanchao Xu
Chun Jason Xue
Published in:
SAC (2016)
Keyphrases
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memory access
main memory
embedded processors
memory hierarchy
multithreading
query processing
parallel processing
parallel tree search
parallel algorithm
memory subsystem
multiprocessor systems
back end
cache management
database systems
message passing
data access
data structure