A triple port RAM based low power commutator architecture for a pipelined FFT processor.
Mohd. HasanTughrul ArslanPublished in: ISCAS (5) (2003)
Keyphrases
- low power
- high speed
- single chip
- vlsi architecture
- power consumption
- low cost
- parallel architecture
- gate array
- cmos technology
- mixed signal
- nm technology
- design considerations
- logic circuits
- signal processor
- data flow
- printed circuit
- low power consumption
- digital signal processing
- instruction set
- management system
- data conversion
- random access memory
- image sensor
- floating point
- parallel processing
- databases
- real time
- database
- instruction set architecture
- power reduction
- multithreading
- processing elements
- design methodology