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Minimum adder-delay architecture of 8/16/32-point DCT based on fixed-rotation adaptive CORDIC.
Trong-Thuc Hoang
Duc-Hung Le
Cong-Kha Pham
Published in:
IEICE Electron. Express (2018)
Keyphrases
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data flow
fpga implementation
image compression
software architecture
real time
management system
learning capabilities
image sequences
rotation invariant
network architecture
parallel architecture
scale factor
mpeg video
digital computer