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Design of new full adder cell using hybrid-CMOS logic style.

Mohammad Javad ZavareiMohammad Reza BaghbanmaneshEhsan KargaranHooman NabovatiAbbas Golmakani
Published in: ICECS (2011)
Keyphrases
  • logic circuits
  • chip design
  • user interface
  • low power
  • data sets
  • e learning
  • power dissipation
  • high speed
  • logic programming
  • case study
  • power consumption
  • hybrid learning
  • delay insensitive