A Hardware Architecture for Reconfigurable Intelligent Surfaces with Minimal Active Elements for Explicit Channel Estimation.
George C. AlexandropoulosEvangelos VlachosPublished in: CoRR (2020)
Keyphrases
- hardware architecture
- hardware implementation
- channel estimation
- field programmable gate array
- communication systems
- multipath
- cdma systems
- hardware architectures
- ofdm system
- fading channels
- signal processing
- estimation algorithm
- frequency selective
- bit error rate
- embedded systems
- efficient implementation
- image processing algorithms
- parallel computing
- associative memory
- shortest path
- general purpose