An 8.5-ps Two-Stage Vernier Delay-Line Loop Shrinking Time-to-Digital Converter in 130-nm Flash FPGA.

Jie Zhang Dongming Zhou

Published in: IEEE Trans. Instrum. Meas. (2018)

Keyphrases

data conversion
high speed
real time
low cost
data acquisition
digital content
metal oxide semiconductor
closed loop
digital media
field programmable gate array
single chip
hardware architecture
digital signal processing
power electronics