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Fully integrated CMOS phase-locked loop with 15 to 240 MHz locking range and ∓50 ps jitter.

Ilya I. NovofJohn AustinRam KelkarDon StrayerSteve Wyatt
Published in: IEEE J. Solid State Circuits (1995)
Keyphrases
  • decision making
  • fully integrated
  • high speed
  • phase locked loop
  • cmos technology
  • power consumption
  • low power
  • concurrency control
  • case study
  • object oriented
  • workflow management
  • nm technology