An Efficient STT-RAM Last Level Cache Architecture for GPUs.

Mohammad Hossein Samavatian Hamed Abbasitabar Mohammad Arjomand Hamid Sarbazi-Azad

Published in: DAC (2014)

Keyphrases

memory access
main memory
prefetching
higher level
design considerations
query processing
management system
data access
memory hierarchy
real time
data structure
operating system
highly efficient
computational power
multithreading