Comparative evaluation of Body Biasing and Voltage Scaling for Low-Power Design on 28nm UTBB FD-SOI Technology.
Ricardo Gomez GomezEdwige BanoSylvain ClercPublished in: ISLPED (2019)
Keyphrases
- low power
- cmos technology
- comparative evaluation
- nm technology
- low voltage
- silicon on insulator
- power consumption
- gate array
- low cost
- high speed
- single chip
- low power consumption
- vlsi architecture
- logic circuits
- power dissipation
- mixed signal
- digital signal processing
- power reduction
- high power
- wireless transmission
- design process
- vlsi circuits
- parallel processing
- cmos image sensor
- ultra low power
- scoring methods
- energy dissipation
- metal oxide semiconductor
- signal processing