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Design of a 1.8V 8-bit 1GSPS cascaded-folding CMOS A/D converter based on a folder averaging technique.
Dongheon Lee
Seunghun Kim
Jooho Hwang
Junho Moon
Minkyu Song
Published in:
SoCC (2009)
Keyphrases
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analog to digital converter
circuit design
case study
single chip
real time
low cost
building blocks
design process
power consumption
low voltage
e learning
email
protein folding
data conversion