Method of RTL Debugging When Using HLS for HW Design : Different Simulation Result of Verilog & VHDL.
Sang Un ParkTae Pyeong KimMee Zee LeeYong Beom ChoPublished in: ISOCC (2018)
Keyphrases
- preprocessing
- simulation study
- cost function
- detection method
- high precision
- high accuracy
- synthetic data
- computational cost
- support vector machine svm
- computationally efficient
- hardware description language
- model based diagnosis
- fully automatic
- classification method
- mathematical model
- clustering method
- optimization algorithm
- data sets
- signal processing
- mobile robot
- prior knowledge
- evolutionary algorithm
- case study
- decision trees
- neural network