Power efficiency benchmarking of a partially reconfigurable, many-tile system implemented on a Xilinx Virtex-6 FPGA.
Raymond J. WeberJustin A. HoganBrock J. LaMeresPublished in: ReConFig (2013)
Keyphrases
- xilinx virtex
- field programmable gate array
- hardware implementation
- hardware architecture
- pipelined architecture
- reconfigurable hardware
- fpga device
- embedded systems
- low cost
- image processing algorithms
- power consumption
- parallel computing
- hardware design
- computing systems
- hardware software
- power reduction
- pattern recognition
- image processing
- low power
- efficient implementation
- real time
- general purpose
- digital signal processing
- wireless sensor networks
- digital signal
- information systems