A High-speed Verilog HDL Simulation Method using a Lightweight Translator.

Ryohei Kobayashi Tomohiro Misono Kenji Kise

Published in: SIGARCH Comput. Archit. News (2016)

Keyphrases

lightweight
high speed
high accuracy
preprocessing
objective function
cost function
segmentation method
high precision
real time
experimental evaluation
support vector machine
clustering method
detection method
significant improvement
feature set
mathematical model