An efficient and low power architecture design for motion estimation using global elimination algorithm.
Yu-Wen HuangShao-Yi ChienBing-Yu HsiehLiang-Gee ChenPublished in: ICASSP (2002)
Keyphrases
- low power
- elimination algorithm
- motion estimation
- high speed
- power consumption
- low cost
- single chip
- hadamard transform
- optical flow
- probabilistic inference
- wireless transmission
- high power
- image sequences
- logic circuits
- motion compensated
- signal processor
- computer vision
- mixed signal
- vlsi architecture
- digital signal processing
- gate array
- reference frame
- motion compensation
- low complexity
- motion vectors
- video sequences
- cmos technology
- variable elimination
- inter frame
- low power consumption
- video coding
- macroblock
- video compression
- vlsi circuits
- super resolution