Efficient implementation of tap delay line filter using high speed Digital Signal Processor.
Muhammad Imran AkramAsrar U. H. SheikhPublished in: ISSPA (2012)
Keyphrases
- efficient implementation
- digital signal processor
- high speed
- real time
- low power
- multi core architecture
- active set
- texas instruments
- hardware implementation
- high speed networks
- real time embedded
- efficient processing
- highly parallel
- filtering algorithm
- block matching motion estimation
- noise reduction
- convergence rate
- low cost