A novel approach to design a digital clock triggered modified pulse latch for 16-bit shift register.

Suraj Pattanaik

Published in: Int. J. Intell. Def. Support Syst. (2020)

Keyphrases

shift register
high speed
random number generator
low power
power consumption
hardware implementation
circuit design
design process
engineering design
real time
real world
case study
feature extraction
low cost
uniform distribution
random number