Pipelined delay-sum architecture based on bucket-brigade devices for on-chip ultrasound beamforming.
Yaowu MoTsunehisa TanakaShigeru AritaAkira TsuchitaniKoji InoueYoshihiko SuzukiPublished in: IEEE J. Solid State Circuits (2003)
Keyphrases
- bucket brigade
- linear array
- reconfigurable hardware
- data flow
- real time
- analog vlsi
- vlsi implementation
- low cost
- function approximation
- mobile devices
- processing elements
- host computer
- ultrasound images
- parallel architecture
- power dissipation
- machine learning
- low power consumption
- hardware architecture
- field programmable gate array
- embedded systems
- level parallelism
- power consumption
- high speed
- active learning
- phase locked loop