Optimized hardware algorithm for integer cube root calculation and its efficient architecture.
Rachmad Vidya Wicaksana PutraTrio AdionoPublished in: ISPACS (2015)
Keyphrases
- detection algorithm
- single pass
- preprocessing
- hardware implementation
- computational complexity
- cost function
- optimization algorithm
- learning algorithm
- computationally efficient
- vlsi implementation
- real time
- high accuracy
- experimental evaluation
- pipeline architecture
- high efficiency
- k means
- hardware architecture
- image processing
- vlsi architecture
- parallel implementation
- convex hull
- times faster
- matching algorithm
- particle swarm optimization
- tree structure
- linear programming
- computational cost
- optimal solution
- objective function
- neural network
- low cost
- worst case
- convergence rate
- recognition algorithm
- dynamic programming
- np hard
- similarity measure
- fpga implementation
- genetic algorithm
- integer arithmetic