A Low-Power and High-PSNR Unified DCT/IDCT Architecture Based on EARC and Enhanced Scale Factor Approximation.
Jianfeng ZhangWei ShiLi ZhouRui GongLei WangHongwei ZhouPublished in: IEEE Access (2019)
Keyphrases
- low power
- scale factor
- low power consumption
- power consumption
- low cost
- high speed
- cmos technology
- image compression
- discrete cosine transform
- single chip
- real time
- image quality
- blocking artifacts
- kalman filter
- differential evolution algorithm
- visual quality
- bit rate
- low bit rate
- image sensor
- dct domain
- storage devices
- high quality