qMC: A Formal Model Checking Verification Framework For Superconducting Logic.
Mustafa MunirAswin GopikannaArash FayyaziMassoud PedramShahin NazarianPublished in: ACM Great Lakes Symposium on VLSI (2021)
Keyphrases
- model checking
- model checker
- verification method
- temporal logic
- bounded model checking
- formal specification
- formal methods
- epistemic logic
- formal verification
- automated verification
- ctl model update
- asynchronous circuits
- temporal epistemic
- temporal properties
- linear time temporal logic
- abstract interpretation
- transition systems
- artifact centric
- linear temporal logic
- reactive systems
- alternating time temporal logic
- symbolic model checking
- ordered binary decision diagrams
- process algebra
- concurrent systems
- modal logic
- timed automata
- bayesian networks
- computation tree logic
- specification language
- worst case