High-performance, low-latency field-programmable gate array-based floating-point adder and multiplier units in a Virtex 4.
Per KarlströmAndreas EhliarDake LiuPublished in: IET Comput. Digit. Tech. (2008)
Keyphrases
- floating point
- low latency
- field programmable gate array
- fpga device
- hardware implementation
- embedded systems
- graphics processing units
- high speed
- fixed point
- high throughput
- parallel computing
- highly efficient
- real time
- image processing algorithms
- hardware architecture
- computing systems
- reconfigurable hardware
- processing units
- stream processing
- hardware software
- floating point arithmetic
- data flow
- virtual machine
- signal processing
- image processing
- parallel architectures
- processing elements
- efficient implementation
- sufficient conditions