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Power-Efficient Pipelined Multiprocessor Architecture With Parallel Trace-Back Mechanism for Multiple Pairwise Sequence Alignment.

Ardhendu SarkarSurajeet Ghosh
Published in: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2024)
Keyphrases
  • sequence alignment
  • pairwise
  • multiprocessor architecture
  • gpu accelerated
  • markov random field
  • parallel architectures
  • multiple sequence alignment
  • data sets
  • similarity measure
  • power consumption
  • binding sites