A design of high-performance pipelined architecture for H.264/AVC CAVLC decoder and low-power implementation.
Byung-Yup LeeKwang-Ki RyooPublished in: IEEE Trans. Consumer Electron. (2010)
Keyphrases
- low power
- low power consumption
- vlsi architecture
- low complexity
- cmos technology
- power consumption
- low cost
- single chip
- signal processor
- video decoder
- logic circuits
- high speed
- ultra low power
- gate array
- vlsi implementation
- deblocking filter
- video codec
- real time
- design methodology
- efficient implementation
- mixed signal
- video coding
- signal processing
- hardware implementation
- embedded systems
- image processing