A General Model Checking Framework for Various Memory Consistency Models.

Tatsuya Abe Toshiyuki Maeda

Published in: IPDPS Workshops (2014)

Keyphrases

model checking
temporal logic
artifact centric
reactive systems
formal verification
finite state machines

model checker
finite state
pspace complete
temporal properties
bounded model checking

reachability analysis
abstract interpretation
asynchronous circuits
ordered binary decision diagrams
concurrent systems

partial order reduction
automated verification
verification method
formal specification
epistemic logic