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Codevelopment of multi-level instruction set architecture and hardware for an efficient matrix processor.
Mostafa I. Soliman
Abdulmajid F. Al-Junaid
Published in:
Neural Parallel Sci. Comput. (2010)
Keyphrases
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instruction set
instruction set architecture
computer architecture
floating point
ibm power processor
low cost
application specific
single chip
embedded systems
ibm zenterprise
high end
multi core processors
real time
parallel architectures
high volume
data objects
processor core
computer systems
database