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Hardware implementation of the quasi-maximum likelihood estimator core for polynomial phase signals.
Nevena R. Brnovic
Igor Djurovic
Veselin N. Ivanovic
Marko Simeunovic
Published in:
IET Circuits Devices Syst. (2019)
Keyphrases
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hardware implementation
maximum likelihood estimator
signal processing
maximum likelihood
efficient implementation
software implementation
fpga implementation
field programmable gate array
dedicated hardware
pattern recognition
image processing algorithms
general purpose processors
computer vision
text mining