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A 256-channel multi-phase clock sampling-based time-to-digital converter implemented in a Kintex-7 FPGA.
Yonggang Wang
Peng Kuang
Chong Liu
Published in:
I2MTC (2016)
Keyphrases
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fpga device
high speed
data conversion
analog to digital converter
single phase
multi channel
real time image processing
hardware implementation
pipelined architecture
motion planning
real time
monte carlo
low cost
wireless channels
input output
mobile robot
image processing