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Transistor-Level Gate Modeling for Nano CMOS Circuit Verification Considering Statistical Process Variations.

Qin TangAmir ZjajoMichel BerkelaarNick van der Meijs
Published in: PATMOS (2010)
Keyphrases
  • high speed
  • circuit design
  • cmos technology
  • low power
  • low cost
  • analog vlsi
  • statistical analysis
  • power dissipation
  • colored petri nets
  • nano scale
  • real time
  • process model
  • power consumption
  • integrated circuit