A high speed and low power 4∶1 multiplexer with cascoded clock control.

Jin-Hyoung Park Ji-Seop Song Shin-Il Lim Suki Kim

Published in: APCCAS (2010)

Keyphrases

low power
high speed
power consumption
single chip
high power
real time
frame rate
wireless transmission
logic circuits
low cost
digital signal processing
vlsi circuits
vlsi architecture
cmos technology
low power consumption
power reduction
image sensor
motion estimation