A Low-Power Arithmetic Element for Multi-Base Logarithmic Computation on Deep Neural Networks.

Jiawei Xu Yuxiang Huan Li-Rong Zheng Zhuo Zou

Published in: SoCC (2018)

Keyphrases

low power
neural network
power consumption
low cost
high speed
single chip
high power
logic circuits
wireless transmission
vlsi architecture
digital signal processing
low power consumption
cmos technology
pattern recognition
real time
power reduction
vlsi circuits
image sensor
video sequences
pipelined architecture