A High Packing Density Module Generator for CMOS Logic Cells.

Yoichi Shiraishi Jun'ya Sakemi Makoto Kutsuwada Akira Tsukizoe Takashi Satoh

Published in: DAC (1988)

Keyphrases

delay insensitive
wide range
high speed
low cost
data sets
classical logic
real time
modal logic
automated reasoning
asynchronous circuits
low density
random access memory