A parallel compensated Horner scheme for SIMD architecture.
Stef GraillatYouness IbrahimyClothilde JeangoudouxChristoph Quirin LauterPublished in: ARITH (2023)
Keyphrases
- processor array
- single instruction multiple data
- parallel processing
- parallel architecture
- parallel implementation
- massively parallel
- array processor
- parallel computers
- parallel algorithm
- distributed processing
- processing elements
- master slave
- parallel architectures
- multi processor
- highly parallel
- parallel computing
- processing units
- management system
- real time
- peer to peer
- computer architecture
- level parallelism
- detection scheme
- shared memory
- mesh connected
- software architecture
- model based predictive control
- distributed memory
- vlsi implementation
- parallel computation
- network architecture
- general purpose
- multi agent systems
- neural network