Dynamic Instruction Scheduling in a Trace-based Multi-threaded Architecture.

Peter Rounce Alberto Ferreira de Souza

Published in: Int. J. Parallel Program. (2008)

Keyphrases

multi threaded
multithreading
instruction scheduling
multi core processors
highly efficient
parallel computing
real time
computational power
operating system
information flow
distributed memory
memory efficient
neural network
multi layer
shared memory