High performance VLSI architecture of fractional motion estimation in H.264 for HDTV.
Changqi YangSatoshi GotoTakeshi IkenagaPublished in: ISCAS (2006)
Keyphrases
- vlsi architecture
- motion estimation
- low complexity
- vlsi implementation
- low power
- video coding
- real time
- high definition
- image sequences
- video sequences
- video compression
- motion vectors
- motion compensation
- motion compensated
- inter frame
- super resolution
- reference frame
- optical flow
- video conferencing
- motion field
- spatial domain
- computational complexity
- low cost
- rate distortion
- computer vision
- high speed
- coding efficiency
- distributed video coding
- wavelet transform
- macroblock
- moving objects
- mode decision
- neural network