A 0.8V 875 MS/s 7b low-power SAR ADC for ADC-Based Wireline Receivers in 22nm FDSOI.
David CordovaWim CopsYann DevalFrancois RivetHervé LapuyadeNicolas NodenotYohan PiccinPublished in: VLSI-SOC (2020)
Keyphrases
- low power
- single chip
- low cost
- power consumption
- high speed
- analog to digital converter
- cmos technology
- wide dynamic range
- digital signal processing
- high power
- vlsi circuits
- wireless transmission
- mixed signal
- power reduction
- nm technology
- vlsi architecture
- low power consumption
- synthetic aperture radar
- logic circuits
- high resolution
- sar images
- wireless networks
- wireless communication
- image sensor
- parallel processing
- signal processor
- digital camera