Design Margin Reduction Through Completion Detection in a 28-nm Near-Threshold DSP Processor.

Roel Uytterhoeven Wim Dehaene

Published in: IEEE J. Solid State Circuits (2022)

Keyphrases

support vector
high speed
design process
verilog hdl
real time
case study
objective function
user interface
computer aided
automatic detection
parallel processing
engineering design
training set
signal processing
detection method
detection accuracy