Low-power hardware for neural spike compression in BMIs.
Angelo C. LapolliBertrand CoppaRodolphe HéliotPublished in: EMBC (2013)
Keyphrases
- low power
- low cost
- single chip
- vlsi architecture
- spike trains
- high speed
- power consumption
- low power consumption
- digital signal processing
- spiking neurons
- hardware and software
- image sensor
- network architecture
- power reduction
- signal processor
- real time
- gate array
- high power
- compression algorithm
- neuronal networks
- wireless transmission
- embedded systems
- vlsi circuits
- image compression
- logic circuits
- hodgkin huxley
- signal processing
- compression ratio
- mixed signal
- random access
- bio inspired
- computer systems
- vlsi implementation
- spiking neural networks
- digital camera
- lossy compression
- action potentials
- computing systems
- hardware implementation